1. Field of the Invention
The present invention relates to an EEPROM apparatus which consists of EEPROM and attached equipment and in which a so-called checker pattern test is performed in order to guarantee the reliability of the EEPROM, and more specifically to an EEPROM apparatus built, for example, in a one-chip microcomputer used for an IC card.
2. Description of Related Art
FIG. 1 is a functional block diagram showing a conventional general functional configuration of a one-chip microcomputer in which EEPROM are built in, showing specifically a configuration of a so-called five-terminal type IC card.
In FIG. 1, reference numeral 1 designates a CPU which processes data according to a user program. The user program processed by this CPU 1 is stored in a ROM 2. Among the data processed by the CPU 1, data which is necessary to be temporarily stored is stored in a RAM 3. The CPU 1, the ROM 2 and the RAM 3 are connected to each other by a bus 14.
Reference numeral 4 designates an input/output control circuit which is connected between the bus 14 and an I/O terminal 13 among external connection terminals shown by reference numerals 9 to 13. The input/output control circuit 4 converts serial data inputted from the outside to parallel data to output the parallel data to the bus 14, and converts parallel data given from the bus 14 to serial data to output the serial data via the I/O terminal 13 to the outside.
Reference numeral 5 designates an EEPROM apparatus which is composed of an EEPROM as a programmable data memory designated by numeral 50, an ECC (Error Checking and Correction) circuit 6, an EEPROM 7 for ECC circuit, a data latch circuit 8, and the like.
The EEPROM 50 stores data necessary to be always stored such as data being a processing result by the CPU 1.
The ECC circuit 6 generates an error correction code (ECC code) of data inputted from the bus 14 and stored in the EEPROM 50 and makes the EEPROM 7 for ECC circuit store the ECC code. When data stored in the EEPROM 50 is read out, the ECC circuit 6 outputs the corresponding ECC code from the EEPROM 7 for ECC circuit to the bus 14.
The EEPROM 7 for ECC circuit stores an ECC code generated by the ECC circuit 6 and outputs it to the bus 14 as occasion demands.
And the data latch circuit 8 latches data to be written in the EEPROM 50 and an ECC code generated by the ECC circuit 6.
In addition, in the conventional EEPROM apparatus shown in FIG. 1, memory cells are arranged in the state of matrix in eight-bit width in the EEPROM 50 and one eight-bit data is stored in each row of eight-bit width. While in the EEPROM 7 for ECC circuit, memory cells are arranged in the state of matrix in four-bit width, and one ECC code is stored in each row of four-bit width. But both the EEPROM 50 and the EEPROM 7 are integrated in terms of hardware. When memory cells are assumed to be arranged in the state of matrix in n-bit width in one EEPROM 500. Generally speaking, m bits among n bits and the remaining "n-m" bits in each row of the EEPROM 500 are shared properly by the EEPROM 50 and the EEPROM 7 for ECC circuit.
Accordingly, when data is stored in the EEPROM 50, an ECC code of the data is stored in the row of the EEPROM 7 for ECC circuit being same row of the EEPROM 50 in which the data is stored. In other words, one data of m bits and the ECC code of the data of "n-m" bits are sequentially stored in one row of n bits of the EEPROM 500 constructing the EEPROM 50 and the EEPROM 7 for ECC circuit.
Reference numeral 9 to 13 designates the external connection terminals, as aforementioned, and numeral 9 designates power source (Vcc) terminal to which power source voltage is supplied, numeral 10 designates a ground (GND) terminal to which ground potential is connected, numeral 11 designates a reset (RST) terminal to which reset, signal is inputted, numeral 12 designates a clock (CLK) terminal to which operation clock of this microcomputer is supplied, and numeral 13 designates the I/O terminal to and from which serial data is inputted/outputted, as aforementioned.
When the one-chip microcomputer for IC card shown in FIG. 1 is inserted in a proper apparatus, these external connection terminals 9 to 13 are connected to terminals of the side of the apparatus.
FIG. 2 is a circuit diagram showing a schematic circuit configuration of the aforementioned ECC circuit 6. In FIG. 2, a portion designated by reference numeral 15 is an ECC code generating unit which inputs eight-bit write data DB0 to DB7 to be stored in the EEPROM 50 and generates a four-bit ECC code. In addition, the eight-bit write data DB0 to DB7 is originally the data to be written in the EEPROM 50 from the bus 14 through the data latch circuit 8, however, the same data is also given to the ECC circuit 6 from the bus 14 and an ECC code is generated by the ECC code generating unit 15.
Reference numeral 16 designates a switching circuit which selectively out,puts either an ECC code generated by the ECC code ,generating unit 15 or signals of four bits D0 to D3 given from the CPU 1 outside of the EEPROM apparatus 5 through the bus 14.
The switching circuit 16 is controlled by a control signal WR 18 given from the CPU 1, however, when the control signal WR 18 is in the high level, it outputs the signals of four bits D0 to D3 inputt, ed from the outside, and when the control signal WR 18 is in the low level, it outputs an ECC code generated by the ECC code generating unit 15, selectively. The signals EB8 to EB11 outputted from the switching circuit 16 is given as an EGG code 17 to the EEPROM 7 For ECC circuit through the data latch circuit 8 and stored.
By the way, the ECC code generating unit, 15 consists of four groups of ECC code generating circuits 151 to 154 in order to generate ECC code of four bits. In addition, each of the ECC code generating circuits 151 to 154 is composed of four two-input EXNOR gates.
At the first ECC code generating circuit 151, to an EXNOR gate 151a, the bit DB0 and the bit DB1 are inputted, to an EXNOR gate 151b, the output signal of the EXNOR gate 151a and the bit DB3 are inputted, to an EXNOR gate 151c, the output signal of the EXNOR gate 151b and the bit DB4 are inputted, and to an EXNOR gate 151d, the output signal of the EXNOR gate 151c and the bit DB6 are inputted.
At the second ECC code generating circuit 152, to an EXNOR gate 152a, the bit DB0 and the bit DB2 are inputted, to an EXNOR gate 152b, the output signal of the EXNOR gate 152a and the bit DB3 are inputted, to an EXNOR gate 152c, the output signal of the EXNOR gate 152b and the bit DB5 are inputted, and to an EXNOR gate 152d, the output signal of the EXNOR gate 152c and the bit DB6 are inputted.
At the third ECC code generating circuit 153, to an EXNOR gate 153a, the bit DB1 and the bit DB2 are inputted, to an EXNOR gate 153b, the output of the EXNOR gate 153a and the bit DB3 are inputted, to an EXNOR gate 153c, the output signal of the EXNOR gate 153b and the bit DB7 are inputted, and to an EXNOR gate 153d, the output signal of the EXNOR gate 153c and the bit DB0 are inputted.
At the fourth ECC code generating circuit 154, to an EXNOR gate 154a, the bit DB4 and the bit DB5 are inputted, to an EXNOR gate 154b, the output signal of the EXNOR gate 154a and the bit DB6 are inputted, to an EXNOR gate 154c, the output signal of the EXNOR gate 154b and the bit DB7 are inputted, and to an EXNOR garde 154d, the output signal of the EXNOR gate 154c and the bit DB0 are inputted.
FIG. 3 is a block diagram showing a configuration of the data latch circuit 8. The data latch circuit 8 has a 12-bit configuration, and latches the aforementioned EB8 to EB11 of four-bit ECC code and DB0 to DB7 of eight-bit data, and a circuit for each one bit is composed of a general latch circuit in which two inverters are inverse-parallel-connected, as designated by numeral 20.
By the way, in the one-chip microcomputer in which such EEPROM 500 constituted by the EEPROM 50 and EEPROM 7 is built in, it is necessary to perform checker pattern test of the EEPROM 500. The checker pattern test is the one by which whether each memory cell constructing the EEPROM is affected by memory cell adjacent to it or not is checked. Specifically, data ("1" or "0") different from that of four memory cells which are adjacent, in the orthogonal direction of matrix, to each of the memory cells of the EEPROM arranged in the state of matrix is stored, then read it, thereby it is checked whether each of the memory cells is affected by the data stored in memory cell adjacent to each of the memory cells or not.
An actual procedure of this checker pattern test is performed as follows, as an example.
For example, when "55(H)" ((H) represents hexadecimal number) as data, that is, "01010101(B)" ((B) represents binary number) is written in the EEPROM 50, each of the digital values thereof, "0", "1", "0", "1", "0", "1", "0", "1" are stored in a row of eight-bit width of the EEPROM 50 sequentially as DB7, DB6, DB5, DB4, DB3, DB2, DB1 , DB0. At the same time, by each of the ECC code generating circuits 151 to 154 of the ECC code generating unit 15, "B(H)", that is, "1011(B)" is generated as an ECC code 17, and the respective digital values thereof, "1", "0", "1", "1" are stored in a row of four-bit width of the EEPROM 7 for ECC circuit sequentially as ECC code EB11, EB10, EB9, EB8.
And when "AA(H)", that is, "10101010(B)", for example, is written as data in the EEPROM 50, the respective digital values thereof, "1", "0", "1", "0", "1", "0", "1", "0" are stored in a row of eight-bit width of the EEPROM 50 sequentially as data DB7, DB6, DB5, DB4 , DB3, DB2, DB1, DB0. At the same time, by each of the ECC code generating circuits 151 to 154 of the ECC code generating unit 15, "6(H)", that is, "0110(B)" is generated as the ECC code 17, and the respective digital values thereof, "0", "1", "1", "0" are stored sequentially in a row of four-bit width of the EEPROM 7 for ECC circuit as ECC code EB11, EB10, EB9, EB8.
Accordingly, when such two kinds of data "55(H)" and "AA(H)" as aforementioned in which "1(B)" and "1(B)" are arranged alternately are written alternately, since their digital values are written intact in the EEPROM bit 50, data stored in a memory cell adjacent to each other of the EEPROM 50 always has a combination of "1(B)" and "0(B)". On the other hand, in the EEPROM 7 for ECC circuit, data of ECC code in which "1(B)" and "0(B)" are not always arranged alternately, not like the aforementioned, is stored. Therefore, by making the control signal WR 18 be in the high level so that data from the outside is inputted to the switching circuit 16, data is written in the EEPROM 7 for ECC circuit separately by the CPU 1.
That is, as D0 to D3, "5(H)",that is, "0101(B)" and "A(H)", that is, "1010(B)" are inputted alternately in the switching circuit 16 so that they are stored in the EEPROM 7 for ECC circuit. Thereby, data stored in a memory cell adjacent to the EEPROM 7 for ECC circuit always has a combination of "1(B)" and "0(B)", and also when the EEPROM 50 and EEPROM 7 are regarded as an integral hardware as the EEPROM 500, data stored in an adjacent memory cell always has a combination of "1(B)" and "0(B)", too.
In addition, when data is written to the aforementioned EEPROM 50 and the EEPROM 7 for ECC circuit, each data is written in the EEPROM 50 or the EEPROM 7 for ECC circuit after being latched temporarily in the data latch circuit 8.
As aforementioned, in an EEPROM of a conventional one-chip microcomputer, data has to be written separately in the EEPROM 50 and the EEPROM 7 for ECC circuit of the EEPROM 500 when checker pattern test is performed, there is such a problem that the checker pattern test is complicated and require a lot of time.